Catalogo dei prodotti della ricerca

OLIVIERI, Mauro
 Distribuzione geografica
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Continente #
NA - Nord America 6.653
EU - Europa 2.595
AS - Asia 952
SA - Sud America 27
AF - Africa 11
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 2
Totale 10.242
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Nazione #
US - Stati Uniti d'America 6.607
IT - Italia 850
SG - Singapore 418
DE - Germania 416
SE - Svezia 416
IN - India 283
UA - Ucraina 271
FI - Finlandia 199
CN - Cina 169
GB - Regno Unito 114
RU - Federazione Russa 91
AT - Austria 40
CA - Canada 39
NL - Olanda 37
IE - Irlanda 32
BG - Bulgaria 30
RO - Romania 27
ID - Indonesia 22
FR - Francia 19
AR - Argentina 18
KR - Corea 17
ES - Italia 12
TR - Turchia 10
BE - Belgio 9
RS - Serbia 9
MX - Messico 7
VN - Vietnam 7
HK - Hong Kong 6
BR - Brasile 5
PL - Polonia 5
TW - Taiwan 5
ZA - Sudafrica 5
CL - Cile 4
JP - Giappone 4
LU - Lussemburgo 4
CH - Svizzera 3
LT - Lituania 3
MY - Malesia 3
AE - Emirati Arabi Uniti 2
CZ - Repubblica Ceca 2
EU - Europa 2
LB - Libano 2
TG - Togo 2
AU - Australia 1
DK - Danimarca 1
EE - Estonia 1
GR - Grecia 1
IR - Iran 1
KH - Cambogia 1
LV - Lettonia 1
MA - Marocco 1
ME - Montenegro 1
MU - Mauritius 1
NO - Norvegia 1
NZ - Nuova Zelanda 1
PS - Palestinian Territory 1
SC - Seychelles 1
TH - Thailandia 1
TN - Tunisia 1
Totale 10.242
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Città #
Fairfield 1.113
Woodbridge 556
Ashburn 493
Houston 440
Seattle 418
Chandler 400
Rome 358
Wilmington 353
Cambridge 347
Santa Clara 332
Singapore 291
Ann Arbor 256
Princeton 192
San Paolo di Civitate 171
Plano 158
Lawrence 117
Beijing 95
Jacksonville 86
Boston 76
Des Moines 73
Millbury 66
San Diego 66
Boardman 59
Helsinki 59
Andover 48
New York 42
Norwalk 39
Vienna 36
Milan 35
Dublin 32
Sofia 30
Southend 28
Toronto 27
Falkenstein 26
Falls Church 20
Jakarta 20
Dearborn 19
Federal 18
Agropoli 15
Bühl 15
London 14
Nanjing 14
Westminster 13
Ottawa 11
Istanbul 10
Meppel 10
Belgrade 9
Brussels 9
Kunming 9
Moscow 8
Redwood City 8
Aprilia 7
Auburn Hills 7
Buffalo 7
Mannheim 7
Phoenix 7
Turin 7
Cagliari 6
Hefei 6
Hong Kong 6
San Mateo 6
Bologna 5
Fuzhou 5
Los Angeles 5
Philadelphia 5
Barcelona 4
Commerce City 4
Florence 4
Genoa 4
Guangzhou 4
Ho Chi Minh City 4
Krakow 4
Lappeenranta 4
Laurel 4
Luxembourg 4
Mexico 4
Naples 4
Redmond 4
St Petersburg 4
Uffing 4
Bari 3
Bilbao 3
Casandrino 3
Duncan 3
Frascati 3
Geneva 3
Genova 3
Grenoble 3
Hanoi 3
Hanover 3
Indiana 3
Isola Della Scala 3
Jinan 3
Kilburn 3
Kleve 3
Lodi 3
Madrid 3
Nagamineminami 3
New Bedfont 3
Preganziol 3
Totale 7.346
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Nome #
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells 157
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs 151
Dosimetric characterization of an irradiation set-up for electronic components testing at the TOP-IMPLART proton linear accelerator 150
Current controlled current conveyor (CCCII) and application using 65nm CMOS technology 139
Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations 138
Optimal transistor sizing for maximum yield in variation-aware standard cell design 130
Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell 128
Sizing and optimization of low power process variation aware standard cells 127
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions 120
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) 117
EFFICIENT SEMICUSTOM MICROPIPELINE DESIGN 112
A novel logic level calculation model for leakage currents in digital nano-CMOS circuits 112
LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits 112
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique 109
SPECTRAL ESTIMATION FOR 2-D DOPPLER ULTRASOUND IMAGING 104
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops 101
Testing power-analysis attack susceptibility in Register Transfer Level designs 100
BLOCK PLACEMENT WITH A BOLTZMANN MACHINE 98
MPARM: Exploring the multi-processor SoC design space with SystemC 96
Impact of approximate memory data allocation on a H.264 software video encoder 95
A platform-based emulator for mass-storage flash cards evaluation in embedded systems 93
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer 93
Fuzzy Logic Micro-Controller 92
Statistical carry lookahead adders 92
Yield optimization for low power current controlled current conveyor 91
AppropinQuo: a platform emulator for exploring the approximate memory design space 90
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops 87
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores 86
Approximate memory support for Linux early allocators in ARM architectures 85
Synthesis time reconfigurable floating point unit for transprecision computing 85
Design of synchronous and asynchronous variable-latency pipelined multipliers 85
DESIGN AND CHARACTERIZATION OF A STANDARD CELL SET FOR DELAY INSENSITIVE VLSI DESIGN 84
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores 84
A reconfigurable, low power, temperature compensated IC for 8-segment gamma correction curve in TFT, OLED and PDP displays 83
Introducing approximate memory support in Linux Kernel 83
Hardware design of asynchronous fuzzy controllers 82
An emulator for approximate memory platforms based on QEmu 81
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores 79
Elementi di Progettazione dei Sistemi VLSI - Vol 1 - Introduzione all'elettronica digitale 79
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment 79
A class of code compression schemes for reducing power consumption in embedded microprocessor systems 78
HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures 78
Full system emulation of approximate memory platforms with AppropinQuo 78
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes 77
A physical-level LCD driver model and simulator with application to pixel crosstalk suppression 76
Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors 76
Adaptive idleness distribution for non-uniform aging tolerance in multiprocessor systems-on-chip 74
Statistical nonlinear model of MESFET and HEMT devices 74
An asynchronous distributed architecture model for the Boltzmann machine control mechanism 74
A novel high-quality YUV-based image coding technique for efficient image storage in portable electronic appliances 73
Quality aware approximate memory in RISC-V Linux Kernel 72
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating Point Arithmetic Units 71
Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors 71
A standard cell set for delay insensitive VLSI design 71
Instruction level analytic prediction of parallel CPU architecture performance 71
A novel CMOS logic style with data independent power consumption 71
A delay insensitive approach to VLSI design of a DRAM controller 70
A regulation-based security evaluation method for data link in wireless sensor network 70
A low-voltage class-AB OTA exploiting adaptive biasing 70
A self-timed interrupt controller: a case study in asynchronous micro-architecture design 70
Static minimization of total energy consumption in memory subsystem for scratchpad-based systems-on-chips 68
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs 68
Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic 68
An Evaluation System for Distributed-Time VHDL Simulation 67
An Asynchronous Approach to the RISC Design of a Micro-Controller 67
Characterizing noise pulse effects on the power consumption of idle digital cells 67
High level side channel attack modeling and simulation for security-critical systems-on-chips 67
Side channel analysis resistant design flow 67
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor 66
A new algorithm for convergence verification in circuit level simulations 66
Contextual bandits algorithms for reconfigurable hardware accelerators 66
A bootstrap technique for wideband amplifiers 65
Completion-detecting carry select addition 65
Customizable vector acceleration in extreme-edge computing. A risc-v software/hardware architecture study on VGG-16 implementation 65
A non-deterministic scheduler for a software pipelining compiler. 64
Using safe operation regions to assess the error probability of logic circuits due to process variations 64
Optimal pipeline stage balancing in the presence of large isolated interconnect delay 64
A new dynamic differential logic style as a countermeasure to power analysis attacks 64
A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design 63
Yield optimization by means of process parameters estimation: comparison between ABB and ASV techniques 63
A bootstrap technique for wideband amplifiers 62
A post-compiler approach to scratchpad mapping of code 62
A comprehensive analytical model for embedded parallel microprocessors performance prediction 62
Robust three-state PFD architecture with enhanced frequency acquisition capabilities 61
A robust three-state PFD architecture without output polarity reversal 60
Necessary and sufficient conditions for the stability of microwave amplifiers with variable termination impedances 60
Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors 60
Semicustom design of an IEEE 1394-compliant reusable IC core 60
DELAY INSENSITIVE MICRO-PIPELINED COMBINATIONAL LOGIC 60
A model-based methodology to generate code for timer units 60
Design of an ASIC Architecture for High Speed Fractal Image Compression 59
A Parallel Architecture for Color Doppler Flow Technique in Ultrasound Imaging 59
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design 59
A Genetic Approach to The Design Space Exploration of Superscalar Microprocessor Architectures 58
First integration of MOSFET band-to-band-tunneling current in BSIM4 58
Narrowband delay tolerant protocols for WSN applications. Characterization and selection guide 58
Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations 58
VLSI design of a neural processing element for the Boltzmann machine 57
LCD Design Techniques 56
Performance-timing overhead trade-off analysis for a low-power data bus encoding based on input lines reordering 56
Totale 8.073
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Categoria #
all - tutte 29.353
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 29.353
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.623 0 0 0 0 0 265 308 341 306 180 122 101
2020/2021807 71 150 28 61 14 71 9 92 98 131 37 45
2021/20221.669 18 107 173 83 231 42 38 178 115 135 227 322
2022/20231.805 356 444 93 119 173 223 28 112 128 34 45 50
2023/2024832 78 113 46 31 49 93 64 71 11 82 86 108
2024/2025969 100 67 180 177 233 212 0 0 0 0 0 0
Totale 10.562