Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >10(4) speedup versus SPICE.

Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions / Khalid, Usman; Mastrandrea, Antonio; Abbas, Zia; Olivieri, Mauro. - (2015), pp. 1-4. (Intervento presentato al convegno 4th International Conference on Reliability, Infocom Technologies and Optimization, ICRITO 2015 tenutosi a Amity University Uttar Pradesh, ind nel 2015) [10.1109/ICRITO.2015.7359223].

Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions

KHALID, USMAN;MASTRANDREA, ANTONIO;ABBAS, ZIA;OLIVIERI, Mauro
2015

Abstract

Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >10(4) speedup versus SPICE.
2015
4th International Conference on Reliability, Infocom Technologies and Optimization, ICRITO 2015
CMOS; process variations; reliability; VLSI; computer networks and communications; information systems; safety, risk, reliability and quality
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions / Khalid, Usman; Mastrandrea, Antonio; Abbas, Zia; Olivieri, Mauro. - (2015), pp. 1-4. (Intervento presentato al convegno 4th International Conference on Reliability, Infocom Technologies and Optimization, ICRITO 2015 tenutosi a Amity University Uttar Pradesh, ind nel 2015) [10.1109/ICRITO.2015.7359223].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/893110
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