Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions

Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >10(4) speedup versus SPICE.