Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 10 3 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.

LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits / Abbas, Z.; Zahra, A.; Olivieri, M.. - 892:(2019), pp. 394-407. ((Intervento presentato al convegno 22nd International Symposium on VLSI Design and Test, VDAT 2018 tenutosi a Madurai, India [10.1007/978-981-13-5950-7_34].

LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits

Abbas Z.;Zahra A.;Olivieri M.
2019

Abstract

Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 10 3 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.
22nd International Symposium on VLSI Design and Test, VDAT 2018
CMOS; Leakage current; NBTI; PBTI; VHDL
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits / Abbas, Z.; Zahra, A.; Olivieri, M.. - 892:(2019), pp. 394-407. ((Intervento presentato al convegno 22nd International Symposium on VLSI Design and Test, VDAT 2018 tenutosi a Madurai, India [10.1007/978-981-13-5950-7_34].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1292106
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