Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores

FPGA-synthesizable soft-processor cores are commonly used in many digital system applications with low medium production volume, to control heterogeneous dedicated computational units and I/O units. In such contexts, the inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, either as multi-core architecture or multi-threaded single-core. This work presents an experimental exploration of microarchitecture design solutions for multi-threaded soft processor core implementations on FPGA. We report detailed quantitative results on resource utilization, performance and energy efficiency of the different solutions, varying the pipeline organizations, thread pool size, active thread count and voltage.