CHEIKH, ABDALLAH
CHEIKH, ABDALLAH
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
2021 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Vigli, Francesco; Olivieri, Mauro
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer
2020 Blasi, L.; Vigli, F.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration
2022 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro
Contextual bandits algorithms for reconfigurable hardware accelerators
2023 Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro
Customizable vector acceleration in extreme-edge computing. A risc-v software/hardware architecture study on VGG-16 implementation
2021 Sordillo, S.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors
2022 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
2020 Cheikh, A.; Sordillo, S.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors
2020 Cheikh, Abdallah
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
2022 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Ottavi, Marco; Olivieri, Mauro
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
2020 Barbirotta, M.; Mastrandrea, A.; Menichelli, F.; Vigli, F.; Blasi, L.; Cheikh, A.; Sordillo, S.; Di Gennaro, F.; Olivieri, M.
Fault-tolerant hardware acceleration for high-performance edge-computing nodes
2023 Barbirotta, M.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Angioli, M.; Jamili, S.; Olivieri, M.
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy
2023 Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Angioli, Marco; Olivieri, Mauro
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor
2023 Jamili, Saeid; Cheikh, Abdallah; Mastrandrea, Antonio; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro
Improving SET fault resilience by exploiting buffered DMR microarchitecture
2023 Barbirotta, Marcello; Mastrandrea, Antonio; Cheikh, Abdallah; Menichelli, Francesco; Olivieri, Mauro
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores
2017 Olivieri, Mauro; Cheikh, Abdallah; Cerutti, Gianmarco; Mastrandrea, Antonio; Menichelli, Francesco
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores
2021 Cheikh, A.; Sordillo, S.; Mastrandrea, A.; Menichelli, F.; Scotti, G.; Olivieri, M.
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
2019 Cheikh, A.; Cerutti, G.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design | 2021 | Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Vigli, Francesco; Olivieri, Mauro | |
| A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer | 2020 | Blasi, L.; Vigli, F.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Olivieri, M. | |
| Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration | 2022 | Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro | |
| Contextual bandits algorithms for reconfigurable hardware accelerators | 2023 | Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro | |
| Customizable vector acceleration in extreme-edge computing. A risc-v software/hardware architecture study on VGG-16 implementation | 2021 | Sordillo, S.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Olivieri, M. | |
| Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors | 2022 | Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro | |
| Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor | 2020 | Cheikh, A.; Sordillo, S.; Mastrandrea, A.; Menichelli, F.; Olivieri, M. | |
| Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors | 2020 | Cheikh, Abdallah | |
| Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | 2022 | Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Ottavi, Marco; Olivieri, Mauro | |
| Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment | 2020 | Barbirotta, M.; Mastrandrea, A.; Menichelli, F.; Vigli, F.; Blasi, L.; Cheikh, A.; Sordillo, S.; Di Gennaro, F.; Olivieri, M. | |
| Fault-tolerant hardware acceleration for high-performance edge-computing nodes | 2023 | Barbirotta, M.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Angioli, M.; Jamili, S.; Olivieri, M. | |
| Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy | 2023 | Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Angioli, Marco; Olivieri, Mauro | |
| Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor | 2023 | Jamili, Saeid; Cheikh, Abdallah; Mastrandrea, Antonio; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro | |
| Improving SET fault resilience by exploiting buffered DMR microarchitecture | 2023 | Barbirotta, Marcello; Mastrandrea, Antonio; Cheikh, Abdallah; Menichelli, Francesco; Olivieri, Mauro | |
| Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores | 2017 | Olivieri, Mauro; Cheikh, Abdallah; Cerutti, Gianmarco; Mastrandrea, Antonio; Menichelli, Francesco | |
| Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores | 2021 | Cheikh, A.; Sordillo, S.; Mastrandrea, A.; Menichelli, F.; Scotti, G.; Olivieri, M. | |
| The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes | 2019 | Cheikh, A.; Cerutti, G.; Mastrandrea, A.; Menichelli, F.; Olivieri, M. |