CHEIKH, ABDALLAH

CHEIKH, ABDALLAH  

DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI  

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A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design 2021 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Vigli, Francesco; Olivieri, Mauro
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer 2020 Blasi, L.; Vigli, F.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
A RISC-V fault-tolerant soft-processor based on full/partial heterogeneous dual-core protection 2024 Vigli, Francesco; Barbirotta, Marcello; Cheikh, Abdallah; Menichelli, Francesco; Mastrandrea, Antonio; Olivieri, Mauro
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach 2024 Jamili, Saeid; Mastrandrea, Antonio; Cheikh, Abdallah; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro
AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs 2024 Angioli, Marco; Jamili, Saeid; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Rosato, Antonello; Olivieri, Mauro
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration 2022 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro
Contextual bandits algorithms for reconfigurable hardware accelerators 2023 Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro
Customizable vector acceleration in extreme-edge computing. A risc-v software/hardware architecture study on VGG-16 implementation 2021 Sordillo, S.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors 2022 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro
Design, implementation and evaluation of a new variable latency integer division scheme 2024 Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems 2024 Barbirotta, Marcello; Menichelli, Francesco; Cheikh, Abdallah; Mastrandrea, Antonio; Angioli, Marco; Olivieri, Mauro
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor 2020 Cheikh, A.; Sordillo, S.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.
Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors 2020 Cheikh, Abdallah
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core 2022 Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Ottavi, Marco; Olivieri, Mauro
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment 2020 Barbirotta, M.; Mastrandrea, A.; Menichelli, F.; Vigli, F.; Blasi, L.; Cheikh, A.; Sordillo, S.; Di Gennaro, F.; Olivieri, M.
Fault-tolerant hardware acceleration for high-performance edge-computing nodes 2023 Barbirotta, M.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Angioli, M.; Jamili, S.; Olivieri, M.
Heterogeneous tightly-coupled dual core architecture against single event effects 2024 Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Angioli, Marco; Jamili, Saeid; Olivieri, Mauro
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy 2023 Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Angioli, Marco; Olivieri, Mauro
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor 2023 Jamili, Saeid; Cheikh, Abdallah; Mastrandrea, Antonio; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro
Improving SET fault resilience by exploiting buffered DMR microarchitecture 2023 Barbirotta, Marcello; Mastrandrea, Antonio; Cheikh, Abdallah; Menichelli, Francesco; Olivieri, Mauro