A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design

Introducing Fault Tolerance (FT) in designs implemented with commercial-off-the-shelf (COTS) components, such as FPGAs, is very interesting because they are orders of magnitude less expensive than Rad- Hard components. Significant work has been done on FT architectures based on functional redundancy through multi-core processors or Simultaneous Multi Thread (SMT) processors, while very little has been explored in this direction on Interleaved Multi-Threading (IMT) processors. IMT potentially has intrinsic FT features through the redundant execution of the same task on multiple interleaved threads. Also, IMT intrinsically introduces a temporal shift among the redundant instructions, which can be of interest for specific fault situations. Yet, implementing FT within a IMT execution paradigm requires dedicated hardware management. In this work we discuss IMT hardware microarchitecture modifications needed to obtain a stable FT processor, using the RISCV IMT soft-core Klessydra- T13 as the basis of our experiments with an hard Fault-Injection simulation campaign.