Dual-modular-redundancy voting circuits for single-event-transient mitigation

Single Event Transient faults pose an increasing challenge in reliability design especially regarding internal nodes of combinational voting circuits, as device dimensions shrink and working frequencies boost in modern technologies. This work proposes a novel voting structure for Dual Modular Redundancy lock-step architectures, made of a comparator with parity and recovery signal, able to reduce the failure rate down to 6.6% in case of internal SET faults, achieving the lowest value in the literature when compared to the 33% achieved by conventional DMR lock-step comparators and the 68.75% of DMR self-voter approaches without filtering methods. The fault resilience performance comes at the cost of only a slight increase in hardware utilization, power consumption and frequency degradation.