ANGIOLI, MARCO
ANGIOLI, MARCO
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach
2024 Jamili, Saeid; Mastrandrea, Antonio; Cheikh, Abdallah; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro
AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs
2024 Angioli, Marco; Jamili, Saeid; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Rosato, Antonello; Olivieri, Mauro
Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor
2023 Angioli, Marco; Barbirotta, Marcello; Mastrandrea, Antonio; Jamili, Saeid; Olivieri, Mauro
Contextual bandits algorithms for reconfigurable hardware accelerators
2023 Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro
Design, implementation and evaluation of a new variable latency integer division scheme
2024 Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems
2024 Barbirotta, Marcello; Menichelli, Francesco; Cheikh, Abdallah; Mastrandrea, Antonio; Angioli, Marco; Olivieri, Mauro
Fault-tolerant hardware acceleration for high-performance edge-computing nodes
2023 Barbirotta, M.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Angioli, M.; Jamili, S.; Olivieri, M.
Heterogeneous tightly-coupled dual core architecture against single event effects
2024 Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Angioli, Marco; Jamili, Saeid; Olivieri, Mauro
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy
2023 Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Angioli, Marco; Olivieri, Mauro
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor
2023 Jamili, Saeid; Cheikh, Abdallah; Mastrandrea, Antonio; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design
2024 Barbirotta, Marcello; Angioli, Marco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Menichelli, Francesco; Olivieri, Mauro
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach | 2024 | Jamili, Saeid; Mastrandrea, Antonio; Cheikh, Abdallah; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro | |
| AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs | 2024 | Angioli, Marco; Jamili, Saeid; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Rosato, Antonello; Olivieri, Mauro | |
| Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor | 2023 | Angioli, Marco; Barbirotta, Marcello; Mastrandrea, Antonio; Jamili, Saeid; Olivieri, Mauro | |
| Contextual bandits algorithms for reconfigurable hardware accelerators | 2023 | Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro | |
| Design, implementation and evaluation of a new variable latency integer division scheme | 2024 | Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro | |
| Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems | 2024 | Barbirotta, Marcello; Menichelli, Francesco; Cheikh, Abdallah; Mastrandrea, Antonio; Angioli, Marco; Olivieri, Mauro | |
| Fault-tolerant hardware acceleration for high-performance edge-computing nodes | 2023 | Barbirotta, M.; Cheikh, A.; Mastrandrea, A.; Menichelli, F.; Angioli, M.; Jamili, S.; Olivieri, M. | |
| Heterogeneous tightly-coupled dual core architecture against single event effects | 2024 | Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Angioli, Marco; Jamili, Saeid; Olivieri, Mauro | |
| Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy | 2023 | Barbirotta, Marcello; Menichelli, Francesco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Angioli, Marco; Olivieri, Mauro | |
| Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor | 2023 | Jamili, Saeid; Cheikh, Abdallah; Mastrandrea, Antonio; Barbirotta, Marcello; Menichelli, Francesco; Angioli, Marco; Olivieri, Mauro | |
| Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design | 2024 | Barbirotta, Marcello; Angioli, Marco; Mastrandrea, Antonio; Cheikh, Abdallah; Jamili, Saeid; Menichelli, Francesco; Olivieri, Mauro |