Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor

Using Artificial Intelligence (AI) techniques has become the best solution in many applications. By the end of Moore's Law, implementing a platform capable of such massive processing for edge-IoT applications has become a significant challenge. However, using static hardware accelerators can be an excellent solution; even so, they typically require a great deal of silicon area and are not optimized for all operation modes. Reconfigurable computing lets parts of the hardware change proportionally to the task during operation, allowing for optimized operation and the use of many hardware accelerators without requiring a large area. In this study, we present a dynamic acceleration unit exchange on a RISC-V soft-processor based on the open-source Klessydra-T13 RISC-V core. We show how reconfiguration can be used to make the hardware accelerator more flexible and improve its performance. As a case study, we show how reconfiguration techniques can be used to speed up AI architectures by reconfiguration of vector accelerator units.