Special session. SE-UVM, an integrated simulation environment for single event induced failures characterization and its application to the CV32E40P processor

Fault injection tests are created and designed to reproduce real-world faults and errors in controlled environments to evaluate the robustness and reliability of digital systems across various domains. There are three primary types of fault injection mechanisms: simulation-based, hardware emulation-based and physical-based. Each approach presents distinct advantages, challenges, and specific testing requirements and scenarios. In this work, we propose a novel, easy-to-use open-source fault injection simulation environment, written following the Universal Verification Methodology (UVM) Standard, and able to verify any digital design under different fault scenarios like Single Event Upsets (SEU) and Single Event Transients (SET), collecting, and producing as output, failure probabilities on target signals according to five types of output errors, offering detailed insights into the nature and severity of potential failures caused by injected faults. As a case study, we present an integration of this environment on the CV32E40P processor, obtaining an accurate fault injection analysis on the pipeline units for the Helloworld and Coremark benchmarks, with up to more than 23680 faults for each of the 9231 tested architectural bits.