Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy

Dual-core lock-step techniques have emerged as an effective approach to enhance the fault tolerance (FT) capabilities of many safety-critical and mission-critical systems [3, 5], since the probability of faults in digital electronic devices has increased with technology scaling, voltage margin reduction and statistical process variations [6]. While lock-step techniques offer significant advantages, they also come with certain drawbacks related to the implementation of checkpoints and restore methodologies required to save the last correct state of the core and restore it in case of mismatches in the logic due to faults [4]. This paper shows a way of overcoming the disadvantages related to checkpointing and restore methodologies, applying an interleaved execution paradigm inside a dual-core lock-step architecture with a shared redundant Register file, earning in execution time and area overhead.