Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution to maximize the pipeline utilization, when it comes to executing parallel applications, as different threads operate different instruction processing phases in the same cycle. In this study, we expand the target applications of an IMT microarchitecture by introducing an efficient yet handy special-purpose mathematics engine, operating on local scratchpad memories that give low latency and wide data-bus access.
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor / Cheikh, A.; Sordillo, S.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.. - 627:(2020), pp. 529-539. (Intervento presentato al convegno International Conference on Applications in Electronics Pervading Industry, Environment and Society, ApplePies 2019 tenutosi a Pisa, Italia) [10.1007/978-3-030-37277-4_62].
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
Cheikh A.;Sordillo S.;Mastrandrea A.;Menichelli F.;Olivieri M.
2020
Abstract
Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution to maximize the pipeline utilization, when it comes to executing parallel applications, as different threads operate different instruction processing phases in the same cycle. In this study, we expand the target applications of an IMT microarchitecture by introducing an efficient yet handy special-purpose mathematics engine, operating on local scratchpad memories that give low latency and wide data-bus access.| File | Dimensione | Formato | |
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