We propose a novel dynamic CMOS logic style to protect security devices against power attacks. The logic is based on signals with 3 possible states and operates with a power consumption ideally independent of both the logic values and the sequence of data. We have designed a set of logic gates and a flip-flop and compared those to Static Complementary CMOS implementations in terms of correlation between data and power consumption, speed, area, and total power dissipation.
A novel CMOS logic style with data independent power consumption / M., Aigner; S., Mangard; R., Menicocci; Olivieri, Mauro; Scotti, Giuseppe; Trifiletti, Alessandro. - (2005), pp. 1066-1069. (Intervento presentato al convegno IEEE International Symposium on Circuits and Systems (ISCAS) tenutosi a Kobe, JAPAN nel MAY 23-26, 2005) [10.1109/iscas.2005.1464776].
A novel CMOS logic style with data independent power consumption
OLIVIERI, Mauro;SCOTTI, Giuseppe;TRIFILETTI, Alessandro
2005
Abstract
We propose a novel dynamic CMOS logic style to protect security devices against power attacks. The logic is based on signals with 3 possible states and operates with a power consumption ideally independent of both the logic values and the sequence of data. We have designed a set of logic gates and a flip-flop and compared those to Static Complementary CMOS implementations in terms of correlation between data and power consumption, speed, area, and total power dissipation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
