Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical approaches in comparison with SPICE Monte-Carlo verification approach.
Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic / Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro. - (2014), pp. 371-374. (Intervento presentato al convegno 2014 29th International Conference on Microelectronics, MIEL 2014 tenutosi a Belgrade; Serbia) [10.1109/miel.2014.6842167].
Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic
KHALID, USMAN;MASTRANDREA, ANTONIO;OLIVIERI, Mauro
2014
Abstract
Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical approaches in comparison with SPICE Monte-Carlo verification approach.| File | Dimensione | Formato | |
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