Power analysis attacks exploit the existence of "side channels" in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods - such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) - for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential CMOS logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation. © 2008 IEEE.
A new dynamic differential logic style as a countermeasure to power analysis attacks / Giancane, Luca; Marietti, Piero; Olivieri, Mauro; Scotti, Giuseppe; Trifiletti, Alessandro. - (2008), pp. 364-367. (Intervento presentato al convegno 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 tenutosi a St. Julian's nel 31 August 2008 through 3 September 2008) [10.1109/icecs.2008.4674866].
A new dynamic differential logic style as a countermeasure to power analysis attacks
GIANCANE, Luca;MARIETTI, Piero;OLIVIERI, Mauro;SCOTTI, Giuseppe;TRIFILETTI, Alessandro
2008
Abstract
Power analysis attacks exploit the existence of "side channels" in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods - such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) - for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential CMOS logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation. © 2008 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.