Accurate leakage current estimation in the early phase of digital IC synthesis is an increasingly critical step in the design flow. We present a logic-level estimation approach, suitable for implementation in HDL models or as an off-line tool, supporting separate estimation of the leakage components (sub-threshold, gate tunneling, reverse junction BTBT) including pattern dependency, stacking effects and loading effects. Results on single standard cells and multi-cell circuits exhibit a very good accuracy i.e. below 1% error with respect to Spice BSIM4. © 2011 IEEE.
A novel logic level calculation model for leakage currents in digital nano-CMOS circuits / Abbas, Zia; Vanni, Genua; Olivieri, Mauro. - (2011), pp. 221-224. (Intervento presentato al convegno 2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011 tenutosi a Madonna di Campiglio, Trento nel 3 July 2011 - 7 July 2011) [10.1109/prime.2011.5966257].
A novel logic level calculation model for leakage currents in digital nano-CMOS circuits
ABBAS, ZIA;OLIVIERI, Mauro
2011
Abstract
Accurate leakage current estimation in the early phase of digital IC synthesis is an increasingly critical step in the design flow. We present a logic-level estimation approach, suitable for implementation in HDL models or as an off-line tool, supporting separate estimation of the leakage components (sub-threshold, gate tunneling, reverse junction BTBT) including pattern dependency, stacking effects and loading effects. Results on single standard cells and multi-cell circuits exhibit a very good accuracy i.e. below 1% error with respect to Spice BSIM4. © 2011 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
