Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso/Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.
Current controlled current conveyor (CCCII) and application using 65nm CMOS technology / Abbas, Zia; Scotti, Giuseppe; Olivieri, Mauro. - In: WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY. - ISSN 2010-376X. - 79:(2011), pp. 935-939.
Current controlled current conveyor (CCCII) and application using 65nm CMOS technology
ABBAS, ZIA;SCOTTI, Giuseppe;OLIVIERI, Mauro
2011
Abstract
Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso/Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.