The yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations. © 2013 IEEE.
Sizing and optimization of low power process variation aware standard cells / ABBAS, ZIA; KHALID, USMAN; OLIVIERI, Mauro. - (2013), pp. 181-184. (Intervento presentato al convegno 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 tenutosi a South Lake Tahoe; United States nel 13 October 2013 through 17 October 2013) [10.1109/iirw.2013.6804189].
Sizing and optimization of low power process variation aware standard cells
ABBAS, ZIA;KHALID, USMAN;OLIVIERI, Mauro
2013
Abstract
The yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations. © 2013 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
