Clock generator cores play an increasingly important role in the VU1 design of embedded microprocessors supporting specialized power management modes. We present a fully digital. standardcell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 μm CMOS implementation. the circuit features a 16 ps jitter, 19.5-to-79 MHz frequency range with a39KHz input. and less than 50 clock cycles wakeup time. © 2001 IEEE.
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores / Olivieri, Mauro; Trifiletti, Alessandro. - 4:(2001), pp. 638-641. [10.1109/iscas.2001.922318]
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores
OLIVIERI, Mauro;TRIFILETTI, Alessandro
2001
Abstract
Clock generator cores play an increasingly important role in the VU1 design of embedded microprocessors supporting specialized power management modes. We present a fully digital. standardcell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 μm CMOS implementation. the circuit features a 16 ps jitter, 19.5-to-79 MHz frequency range with a39KHz input. and less than 50 clock cycles wakeup time. © 2001 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
