Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)

Process variability are getting worse with the scaled technologies especially below 90 nm, therefore for the reliable fabrication outcome, the effect of both the local and global process variability should be taken into account. In this paper, verification, sizing and design centering/yield optimization for the robust second generation current controlled current conveyor (CCCII+) and CCCII+ based band pass filter for low power without degrading other performances values have been presented. Current conveyors (CC) based applications are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net lists of CCCII+ and band pass filter circuits have been simulated in Eldo using the 65 nm CMOS mixed signal low-K TSMC process development kit (PDK) with 1.2 V, low-Vt devices with statistical models. All analysis, sizing and optimization have been performed using the WiCkeDTM tool at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit. © 2012 Elsevier Ltd. All rights reserved.