Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of 'safe operation region' to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations. © 2013 IEEE.
Using safe operation regions to assess the error probability of logic circuits due to process variations / Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro. - (2013), pp. 177-180. (Intervento presentato al convegno 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 tenutosi a South Lake Tahoe, CA nel 13 October 2013 through 17 October 2013) [10.1109/iirw.2013.6804188].
Using safe operation regions to assess the error probability of logic circuits due to process variations
KHALID, USMAN;MASTRANDREA, ANTONIO;OLIVIERI, Mauro
2013
Abstract
Process variations in conjunction to voltage noise can be responsible of logic errors in digital circuits. The variations in process-induced parameters affect the probability of noise-induced faulty operation of digital logic cells. This work introduces the concept of 'safe operation region' to allow an efficient Monte Carlo evaluation of the associated error probability, avoiding time-consuming circuit level or device level Monte Carlo simulations. © 2013 IEEE.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
