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EnglishA working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investigate the correspondence between theoretical formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We illustrate the new features involved in the electrical design and characterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cells have been fabricated.
http://hdl.handle.net/11573/43151| Titolo: | DESIGN AND CHARACTERIZATION OF A STANDARD CELL SET FOR DELAY INSENSITIVE VLSI DESIGN |
| Autori interni: | OLIVIERI, Mauro |
| Data di pubblicazione: | 1994 |
| Rivista: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. 2, ANALOG AND DIGITAL SIGNAL PROCESSING |
| Abstract: | A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investigate the correspondence between theoretical formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We illustrate the new features involved in the electrical design and characterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cells have been fabricated. |
| Handle: | http://hdl.handle.net/11573/43151 |
| Appare nelle tipologie: | 01.a Pubblicazione su Rivista |
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