Optimal pipeline stage balancing in the presence of large isolated interconnect delay

Pipelining a combinational logic data-path without introducing pipeline stage delay imbalance is a key requirement for efficient digital processing. Balanced pipelining is easily achieved by simple logical effort optimisation when the interconnect and fan-out delay overhead is small and homogeneously distributed. When the target microarchitecture design includes isolated long interconnects, such as buses, optimal pipeline stage balancing becomes a tricky problem. This work formalises the solution based on the logical effort paradigm and evidences its advantage with respect to a heuristic approach.