Catalogo dei prodotti della ricerca

TRIFILETTI, Alessandro
 Distribuzione geografica
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Continente #
NA - Nord America 10.137
EU - Europa 3.188
AS - Asia 1.323
SA - Sud America 87
AF - Africa 20
OC - Oceania 10
Continente sconosciuto - Info sul continente non disponibili 4
Totale 14.769
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Nazione #
US - Stati Uniti d'America 10.030
IT - Italia 1.185
SE - Svezia 604
IN - India 514
SG - Singapore 444
UA - Ucraina 431
CN - Cina 317
FI - Finlandia 240
AT - Austria 196
GB - Regno Unito 160
DE - Germania 98
CA - Canada 91
AR - Argentina 79
IE - Irlanda 63
FR - Francia 62
BG - Bulgaria 45
BE - Belgio 30
RO - Romania 24
NL - Olanda 17
MX - Messico 16
RU - Federazione Russa 12
CH - Svizzera 10
CI - Costa d'Avorio 9
TW - Taiwan 9
IR - Iran 7
KR - Corea 7
AU - Australia 6
PK - Pakistan 6
TR - Turchia 6
GR - Grecia 5
ZA - Sudafrica 5
CL - Cile 4
EU - Europa 4
NZ - Nuova Zelanda 4
PL - Polonia 4
SC - Seychelles 4
BR - Brasile 3
HK - Hong Kong 3
ID - Indonesia 3
LT - Lituania 2
AE - Emirati Arabi Uniti 1
IL - Israele 1
JO - Giordania 1
JP - Giappone 1
KZ - Kazakistan 1
MU - Mauritius 1
MY - Malesia 1
PE - Perù 1
SA - Arabia Saudita 1
TG - Togo 1
Totale 14.769
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Città #
Fairfield 1.747
Woodbridge 811
Ashburn 794
Chandler 728
Seattle 651
Houston 599
Cambridge 544
Wilmington 527
Rome 460
Ann Arbor 452
Princeton 315
Beijing 262
Plano 256
San Paolo di Civitate 242
Singapore 227
Lawrence 196
New York 178
Jacksonville 168
Millbury 164
Vienna 163
Boston 148
San Diego 130
Andover 97
Federal 79
Boardman 76
Dublin 63
Norwalk 54
Des Moines 52
Dearborn 50
Toronto 50
Sofia 45
Southend 45
Milan 39
Mountain View 38
Falls Church 35
Ottawa 34
Brussels 25
Bühl 22
Latina 22
Auburn Hills 21
San Mateo 21
Tivoli 18
Linköping 16
Mannheim 16
London 15
Redwood City 15
Florence 14
Paris 14
Los Angeles 13
Nanjing 11
Redmond 11
Ancona 10
Nuremberg 10
Washington 10
Abidjan 9
Catania 9
L’Aquila 9
Mexico City 9
Hefei 8
Bern 7
Buffalo 7
Ferentino 6
Lardy 6
Marseille 6
Mcallen 6
San Francisco 6
Kunming 5
Medford 5
Banino 4
Calenzano 4
Columbus 4
Daejeon 4
Dallas 4
Delhi 4
Frankfurt am Main 4
Grafing 4
Gussago 4
Helsinki 4
Laurel 4
Muizenberg 4
Palermo 4
Philadelphia 4
Piombino 4
Pune 4
Sant'Anastasia 4
Taichung 4
Adelaide 3
Anzio 3
Arnsberg 3
Auckland 3
Bari 3
Bochum 3
Büdelsdorf 3
Fiesse 3
Formia 3
Genoa 3
Guangzhou 3
Halethorpe 3
Hounslow 3
Incisa 3
Totale 11.015
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Nome #
Calibrating sample and hold stages with pruned Volterra kernels 116
A low-power sample-and-hold circuit based on a switched-opamp technique 110
Testing power-analysis attack susceptibility in Register Transfer Level designs 98
Near-optimum switched capacitor sample-and-hold circuit 97
A 0.6 V class-AB rail-to-rail CMOS OTA exploiting threshold lowering 97
A 0.3 V, rail-to-rail, ultralow-power, non-tailed, body-driven, sub-threshold amplifier 96
A 10 Gb/s CDR in SiGe BiCMOS commercial technology with multistandard capability 94
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology 94
0.9-V CMOS cascode amplifier with body-driven gain boosting 92
CMOS Miller OTA with body-biased output stage 90
Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS 90
Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies 90
A gain-enhancing technique for very low-voltage amplifiers 89
Very low voltage CMOS two-stage amplifier 89
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks 89
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption 85
A sample-and-hold circuit with very low gain error for time interleaving applications 85
Secure double rate registers as an RTL countermeasure against power analysis attacks 84
Switched capacitor sample-and-hold circuit with input signal range beyond supply voltage 84
A high speed truly IC random number source for smart card microcontrollers 83
0.9-V class-AB Miller OTA in 0.35-μm CMOS with threshold-lowered non-tailed differential pair 82
CCII-Based High-Valued Inductance Simulators with minumum Number of Active Elements 81
10-th Order programmable low-pass CMOS integrated pulse-shaping filter 81
Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications 81
A distortion model for pipeline analog-to-digital converters 80
Power-constrained bandwidth optimization in cascaded open-loop amplifiers 80
An active balun for high-CMRR IC design 80
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias 80
High-CMRR current amplifier architecture and its CMOS implementation 79
A bandwidth-compensated transimpedance amplifier for multi-gigabit optical receivers 79
A simple technique for fast digital background calibration of A/D converters 79
A 10 Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability 79
A tree-like amplifier architecture for large gain-bandwidth product 78
Low Voltage CMOS Current and Voltage References Without Resistors 78
Design centering and yield optimisation of MMIC's with off-chip digital controllers 77
A new procedure for non-linear statistical model extraction of GaAs FET integrated circuits 77
A very low-voltage differential amplifier for opamp design 77
Enhancing Power Analysis Attacks against Cryptographic Devices 77
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores 76
CMOS high-CMRR current output stages 76
A countermeasure against differential power analysis based on random delay insertion 75
Analysis and implementation of a minimum-supply body-biased CMOS differential amplifier cell 75
A synthesis-oriented conditional stability criterion for microwave multidevice circuits with complex termination impedances 74
Implementation of the present-80 block cipher and analysis of its vulnerability to side channel attacks exploiting static power 73
A synthesis-oriented approach to design microwave multidevice amplifiers with a prefixed stability margin 72
A fully-differential class-AB OTA with CMRR improved by local feedback 72
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware 71
The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture 71
Calibration of pipeline ADC with pruned Volterra kernels 71
Delay-based dual-rail pre-charge logic 71
A high-speed low-voltage phase detector for clock recovery from NRZ data 71
A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations 70
A novel wake-up receiver with addressing capability for wireless sensor nodes 70
Blind and reference channel-based time interleaved ADC calibration schemes. A comparison 69
Wide-band LNA Design by Parallel FETs 69
A 2-18 GHz monolithic matrix amplifier for low power consumption applications 68
A method for microwave characterization of LiNbO3 modulators 68
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers 68
A novel bias-dependent rational model for MESFET and HEMT devices 68
The Universal Circuit Simulator: A Mixed Signal Approach to n-port Network and Impedance Synthesis 68
Power analysis of chaos-based random number generator for cryptographic security 68
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies 68
CMOS Single to differential Current Amplifier 67
Pinza chirurgica per riconoscere strutture anatomiche 67
Security evaluation and optimization of the delay-based dual-rail pre-charge logic in presence of early evaluation of data 67
Statistical nonlinear model of MESFET and HEMT devices 67
A 10 GHz inductorless active SiGe HBT lowpass filter 67
Model of flicker noise effects on phase noise in oscillators 67
A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate 67
‘Mixed-signal flexible architecture for the synthesis of n-port networks 66
Three-phase dual-rail pre-charge logic 66
An active balun for high-CMRR IC design 66
A low-voltage class-AB OTA exploiting adaptive biasing 66
A compact 3R-receiver module for short-haul SDH STM-16 systems 65
Delay-based dual-rail precharge logic 65
Architecture and modeling of a novel optical beamforming network suitable for microwave photonics implementation 65
VHDL implementation of FWL RLS algorithm 65
Fully integrable current-mode feedback suppressor as an analog countermeasure against CPA attacks in 40nm CMOS technology 65
A novel CMOS logic style with data independent power consumption 65
High level side channel attack modeling and simulation for security-critical systems-on-chips 65
A behavioral model of a noisy VCO for efficient time-domain simulation 64
Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers 64
A flip-flop for the DPA resistant three-phase dual-rail pre-charge logic family 63
Extraction of CAD-compatible statistical non-linear models of GaAs HEMT MMIC’s 63
Implementing radar algorithms on CUDA hardware 63
Side channel analysis resistant design flow 63
A model for the distortion due to switch on-resistance in sample-and-hold circuits 63
Design of stable microwave multi-device circuits with complex termination impedances 62
A class-AB flipped voltage follower output stage 62
A bootstrap technique for wideband amplifiers 62
A Synthesis-Oriented Approach to Design Stable Circuits 62
High-tuning-range CMOS band-pass if filter based on a low-Q cascaded biquad optimization technique 62
88-μ A 1-MHz stray-insensitive CMOS current-mode interface IC for differential capacitive sensors 62
Input-matching and offset-compensation network for limiting amplifiers in optical communication systems 61
Subsampling models of bandwidth mismatch for time-interleaved converter calibration 61
A dynamic and differential CMOS look-up table with data independent power consumption for cryptographic applications on chip cards 61
Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems 60
High-CMRR CMOS current output stage 60
Exploiting the Body of MOS Devices for High Performance Analog Design 60
Yield optimization by means of process parameters estimation: comparison between ABB and ASV techniques 60
Totale 7.405
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Categoria #
all - tutte 43.581
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 377
selected - selezionate 0
volume - volumi 0
Totale 43.958
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20203.439 471 128 69 170 349 394 416 407 381 302 239 113
2020/20211.334 160 166 81 90 84 65 16 120 206 213 99 34
2021/20223.150 128 166 303 72 361 89 92 312 253 253 465 656
2022/20232.968 630 648 150 315 353 262 35 151 180 107 83 54
2023/20241.526 105 199 149 67 98 269 64 57 46 201 121 150
2024/2025148 148 0 0 0 0 0 0 0 0 0 0 0
Totale 15.469