A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f(T) Silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2(23)-1 PRES data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers / A., Pallotta; Centurelli, Francesco; Trifiletti, Alessandro. - STAMPA. - (2000), pp. 67-72. (Intervento presentato al convegno 2000 International Symposium on Low Power Electronics and Design tenutosi a RAPALLO, ITALY nel JUL 26-27, 2000) [10.1109/lpe.2000.876759].
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers
CENTURELLI, Francesco;TRIFILETTI, Alessandro
2000
Abstract
A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f(T) Silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2(23)-1 PRES data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
