The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without affecting the differential-mode behavior; simulations of a sample- A nd-hold exploiting the proposed OTA topology are also presented.

A fully-differential class-AB OTA with CMRR improved by local feedback / Centurelli, F.; Monsurro, P.; Parisi, G.; Tommasino, P.; Trifiletti, A.. - ELETTRONICO. - (2017), pp. 1-4. (Intervento presentato al convegno 2017 European Conference on Circuit Theory and Design, ECCTD 2017 tenutosi a Catania) [10.1109/ECCTD.2017.8093355].

A fully-differential class-AB OTA with CMRR improved by local feedback

Centurelli, F.;Monsurro, P.;Parisi, G.;Tommasino, P.;Trifiletti, A.
2017

Abstract

The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without affecting the differential-mode behavior; simulations of a sample- A nd-hold exploiting the proposed OTA topology are also presented.
2017
2017 European Conference on Circuit Theory and Design, ECCTD 2017
class AB; common-mode; fully differential; operational amplifier; hardware and architecture; electrical and electronic engineering; electronic; optical and magnetic materials
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
A fully-differential class-AB OTA with CMRR improved by local feedback / Centurelli, F.; Monsurro, P.; Parisi, G.; Tommasino, P.; Trifiletti, A.. - ELETTRONICO. - (2017), pp. 1-4. (Intervento presentato al convegno 2017 European Conference on Circuit Theory and Design, ECCTD 2017 tenutosi a Catania) [10.1109/ECCTD.2017.8093355].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1119517
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