On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology

The possibility of recovering sensible information through the observation of dynamic power consumption of a cryptographic device is a critical issue in security applications. As it has been widely demonstrated in the literature, it is possible to reveal the secret keys of a cryptographic device exploiting the information leaked by the implementation through the power side channel. An on-chip, analog, current mode, power consumption equalizer is proposed in this work to overcome the possibility of a successful CPA/DPA attack. The proposed current equalizer circuit allows reducing the variability in the current drawn by a cryptographic CMOS circuit at each clock cycle. This approach allows to avoid full custom logic styles and/or balanced differential routing and can be directly applied to cryptographic devices implemented in standard CMOS logic.