A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.
A sample-and-hold circuit with very low gain error for time interleaving applications / Centurelli, Francesco; Simonetti, Andrea; Trifiletti, Alessandro. - (2007), pp. 456-459. (Intervento presentato al convegno ECCTD European Conference on Circuit Theory and Design tenutosi a Sevilla (Spain) nel 26-30 August 2007) [10.1109/ECCTD.2007.4529631].
A sample-and-hold circuit with very low gain error for time interleaving applications
CENTURELLI, Francesco;SIMONETTI, Andrea;TRIFILETTI, Alessandro
2007
Abstract
A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.| File | Dimensione | Formato | |
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