Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle.
A countermeasure against differential power analysis based on random delay insertion / Bucci, M.; Luzzi, R.; Guglielmo, M.; Trifiletti, A.. - (2006), pp. 3547-3550. (Intervento presentato al convegno ISCAS 05: IEEE International Symposium on Circuits and Systems nel 23-26 May 2005) [10.1109/ISCAS.2005.1465395].
A countermeasure against differential power analysis based on random delay insertion
Luzzi R.;Trifiletti A.
2006
Abstract
Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
