A novel low-power and high-performance sampleand-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-μm CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic cascode operational transconductance amplifier (OTA) to minimize power consumption. Simulation results show that the proposed solution allows simple and reliable S/H function and an effective power reduction without noise and distortion penalty.
A low-power sample-and-hold circuit based on a switched-opamp technique / Centurelli, Francesco; Simonetti, Andrea; Trifiletti, Alessandro. - STAMPA. - (2008), pp. 105-108. (Intervento presentato al convegno ICSES International Conference on Signals and Electronic Systems tenutosi a Krakow (Poland) nel 14-17 September 2008) [10.1109/ICSES.2008.4673369].
A low-power sample-and-hold circuit based on a switched-opamp technique
CENTURELLI, Francesco;SIMONETTI, Andrea;TRIFILETTI, Alessandro
2008
Abstract
A novel low-power and high-performance sampleand-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-μm CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic cascode operational transconductance amplifier (OTA) to minimize power consumption. Simulation results show that the proposed solution allows simple and reliable S/H function and an effective power reduction without noise and distortion penalty.| File | Dimensione | Formato | |
|---|---|---|---|
|
Centurelli_Low-power_2008.pdf
solo gestori archivio
Tipologia:
Versione editoriale (versione pubblicata con il layout dell'editore)
Licenza:
Tutti i diritti riservati (All rights reserved)
Dimensione
208.8 kB
Formato
Adobe PDF
|
208.8 kB | Adobe PDF | Contatta l'autore |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
