In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10μA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has -50dB HD2 and -60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5VPP square wave is about 20ns. © 2011 IEEE.

A class-AB flipped voltage follower output stage / Centurelli, Francesco; Monsurro', Pietro; Trifiletti, Alessandro. - (2011), pp. 786-789. (Intervento presentato al convegno 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011 tenutosi a Linkoping nel 29 August 2011 through 31 August 2011) [10.1109/ecctd.2011.6043851].

A class-AB flipped voltage follower output stage

CENTURELLI, Francesco;MONSURRO', PIETRO;TRIFILETTI, Alessandro
2011

Abstract

In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10μA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has -50dB HD2 and -60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5VPP square wave is about 20ns. © 2011 IEEE.
2011
2011 20th European Conference on Circuit Theory and Design, ECCTD 2011
flipped voltage follower; class-ab; output stage; low power design
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
A class-AB flipped voltage follower output stage / Centurelli, Francesco; Monsurro', Pietro; Trifiletti, Alessandro. - (2011), pp. 786-789. (Intervento presentato al convegno 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011 tenutosi a Linkoping nel 29 August 2011 through 31 August 2011) [10.1109/ecctd.2011.6043851].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/395188
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