Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13μm CMOS technology featuring a signal to noise and distortion ratio (SNDR) of -75dB at 12Ms/s for a 1Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity. ©2009 IEEE.
Near-optimum switched capacitor sample-and-hold circuit / Centurelli, Francesco; Simonetti, Andrea; Trifiletti, Alessandro. - (2009), pp. 1-4. ((Intervento presentato al convegno 2009 NORCHIP tenutosi a Trondheim nel 16 November 2009 through 17 November 2009 [10.1109/norchp.2009.5397857].
Titolo: | Near-optimum switched capacitor sample-and-hold circuit | |
Autori: | ||
Data di pubblicazione: | 2009 | |
Citazione: | Near-optimum switched capacitor sample-and-hold circuit / Centurelli, Francesco; Simonetti, Andrea; Trifiletti, Alessandro. - (2009), pp. 1-4. ((Intervento presentato al convegno 2009 NORCHIP tenutosi a Trondheim nel 16 November 2009 through 17 November 2009 [10.1109/norchp.2009.5397857]. | |
Handle: | http://hdl.handle.net/11573/56210 | |
ISBN: | 9781424443109 | |
Appartiene alla tipologia: | 04b Atto di convegno in volume |
File allegati a questo prodotto
File | Note | Tipologia | Licenza | |
---|---|---|---|---|
Centurelli_Near-optimum_2009.pdf | Versione editoriale (versione pubblicata con il layout dell'editore) | Tutti i diritti riservati (All rights reserved) | Administrator Richiedi una copia |