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EnglishPerformance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13μm CMOS technology featuring a signal to noise and distortion ratio (SNDR) of -75dB at 12Ms/s for a 1Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity. ©2009 IEEE.
http://hdl.handle.net/11573/56210| Titolo: | Near-optimum switched capacitor sample-and-hold circuit |
| Autori interni: | SIMONETTI, Andrea CENTURELLI, Francesco TRIFILETTI, Alessandro |
| Data di pubblicazione: | 2009 |
| Abstract: | Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13μm CMOS technology featuring a signal to noise and distortion ratio (SNDR) of -75dB at 12Ms/s for a 1Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity. ©2009 IEEE. |
| Handle: | http://hdl.handle.net/11573/56210 |
| ISBN: | 9781424443109 |
| Appare nelle tipologie: | 04b Atto di congresso in volume |
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