Distribuzione geografica
Continente #
NA - Nord America 2032
EU - Europa 317
AS - Asia 300
SA - Sud America 7
OC - Oceania 3
AF - Africa 2
Totale 2661
Nazione #
US - Stati Uniti d'America 2006
IN - India 291
SE - Svezia 159
IT - Italia 106
CA - Canada 26
UA - Ucraina 17
GB - Regno Unito 13
RO - Romania 11
ID - Indonesia 6
AR - Argentina 5
DE - Germania 4
BE - Belgio 2
NZ - Nuova Zelanda 2
AT - Austria 1
AU - Australia 1
BR - Brasile 1
EC - Ecuador 1
ES - Italia 1
FR - Francia 1
HK - Hong Kong 1
IE - Irlanda 1
IR - Iran 1
LB - Libano 1
NL - Olanda 1
TG - Togo 1
ZA - Sudafrica 1
Totale 2661
Città #
Fairfield 273
Chandler 186
Princeton 150
Boston 147
Wilmington 119
Houston 90
San Paolo di Civitate 90
Woodbridge 86
Ashburn 82
Cambridge 72
Seattle 69
Andover 53
San Diego 51
Lawrence 45
Norwalk 34
Millbury 25
Toronto 25
Ann Arbor 23
Jakarta 6
Sacramento 6
San Mateo 6
Federal 5
Philadelphia 5
London 4
Redwood City 3
Rome 3
Southend 3
Auckland 2
Brussels 2
Hyderabad 2
Leawood 2
Trumbull 2
Boardman 1
Brisbane 1
Chicago 1
Delhi 1
Dublin 1
Gurgaon 1
Kish 1
Kumar 1
Lanuvio 1
Laurel 1
Le Pré-saint-gervais 1
Linz 1
Lomé 1
Modderfontein 1
Monmouth Junction 1
Montréal 1
Mountain View 1
Porto Alegre 1
Quito 1
Santa Clara 1
Tuen Mun 1
Velletri 1
Totale 1693
Nome #
F-DICE: a multiple node upset tolerant flip-flop for highly radioactive environments 35
XTRA: Towards Portable Transport Layer Functions 30
EMOMA: Exact Match in One Memory Access 30
A Comparative Evaluation of Designs for Reliable Memory Systems 30
A new Hardware/Software platform and a new 1/E neutron source for soft error studies: Testing FPGAs at the ISIS facility 30
Fast Updates for Line-Rate {HyperLogLog} based Cardinality Estimation 29
A fault-tolerant solid state mass memory for highly reliable instrumentation 28
A signed digit adder with error correction and graceful degradation capabilities 27
TupleMerge: Fast Software Packet Processing for Online Packet Classification 27
Flexible Packet Matching with Single Double Cuckoo Hash 27
A QCA memory with parallel read/serial write: design and analysis 27
Efficient implementation of error correction codes in hash tables 26
A reconfigurable functional unit for modular operations 26
A method to construct low delay single error correction codes for protecting data bits only 26
StreaMon : a data-plane programming abstraction for Software-defined Stream Monitoring 26
Error Detection and Correction in SRAM Emulated TCAMs 26
Hardware-Based on-the-fly Per-flow Scan Detector Pre-filter 25
A self-checking cell logic block for fault tolerant FPGAs 25
A fault tolerant hardware based file system manager for solid state mass memory 25
Design of a fault tolerant Solid State Mass Memory 25
A Synergetic use of bloom filters for error detection and correction 25
A class of SEC-DED-DAEC codes derived from orthogonal Latin square codes 25
Europe's First 5G-Ready Railway Trial Utilizing Integrated Optical Passive WDM Access and Broadband Millimeter-Wave to Deliver Multi-Gbit/s Seamless Connectivity 25
Improving Packet Flow Counting With Fingerprint Counting 24
Improving Energy Efficiency of Ethernet Switching with Modular Cuckoo Hashing 24
A Self Checking Reed Solomon Encoder: Design and Analysis 24
Cuckoo Cache a Technique to Improve Flow Monitoring Throughput 24
QCA Circuits for Robust Coplanar Crossing 24
Cuckoo Filters and Bloom Filters: Comparison and Application to Packet Classification 24
Design and analysis of single event tolerant slave latches for enhanced scan delay testing 24
A method to design SEC-DED-DAEC codes with optimized decoding 24
{CFBF}: Reducing the Insertion Time of Cuckoo Filters With an Integrated Bloom Filter 23
2T2M Memristor Based TCAM Cell for Low Power Applications 23
Design of a QCA memory with parallel read/serial write 23
Design of a totally self checking signature analysis checker for finite state machines 23
On the analysis of reed solomon coding for resilience to transient/permanent faults in highly reliable memories 23
A single-bit and double-adjacent error correcting parallel decoder for multiple-bit error correcting BCH codes 23
A method to extend orthogonal latin square codes 23
Timing verification of QCA memory architectures 22
System-on-chip oriented fault-tolerant sequential systems implementation methodology 22
Novel memory designs for QCA implementation 22
Reliability evaluation of repairable/reconfigurable FPGAs 22
Development of a dynamic routing system for a fault tolerant solid state mass memory 22
High-Speed Software Data Plane via Vectorized Packet Processing 22
A method to protect Cuckoo filters from soft errors 22
A length-aware cuckoo filter for faster IP lookup 22
Analysis of errors and erasures in parity sharing RS codecs 22
FlowBlaze: Stateful Packet Processing in Hardware 21
Metronome: Adaptive and precise intermittent packet retrieval in DPDK 21
Novel designs for thermally robust coplanar crossing in QCA 21
Error detection in signed digit arithmetic circuit with parity checker [adder example] 21
Localization of faults in radix-n signed digit adders 21
Evaluating data integrity of memory systems by configurable Markov models 21
Traffic-aware Design of a High Speed FPGA Network Intrusion Detection System 21
Novel complementary resistive switch crossbar memory write and read schemes 21
Concurrent error detection in Reed-Solomon encoders and decoders 21
Adaptive cuckoo filters 21
Error detection in ternary CAMs using bloom filters 20
StreaMon: A software-defined monitoring platform 20
Improving counting Bloom filter performance with fingerprints 20
Efficient flow sampling with back-annotated Cuckoo hashing 20
Analysis and evaluations of reliability of reconfigurable FPGAs 20
An HDL model of magnetic quantum-dot cellular automata devices and circuits 20
Smashing SDN "built-in" actions: programmable data plane packet manipulation in hardware 20
Modeling open defects in nanometric scale CMOS 19
On the use of Signed Digit Arithmetic for the new 6-Inputs LUT based FPGAs 19
Efficient online testing of an array of reconfigurable RISC Processors 19
A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility 19
A Method to Protect Bloom Filters from Soft Errors 19
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction 19
An efficient technique to protect serial shift registers against soft errors 19
OMASS: One Memory Access Set Separation 19
When filtering is not possible caching negatives with fingerprints comes to the rescue 19
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders 18
Concurrent Error Detection in Reed Solomon Decoders 18
Complementary resistive switch based stateful logic operations using material implication 18
Design of a Self Checking Reed Solomon Encoder 18
Error correction codes for SEU and SEFI tolerant memory systems 18
A Novel Write-Scheme For Data Integrity In Memristor-Based Crossbar Memories 18
Data integrity evaluations of Reed Solomon codes for storage systems [solid state mass memories] 18
PR-tcam: Efficient tcam emulation on xilinx FPGAS using partial reconfiguration 18
Low delay single symbol error correction codes based on reed solomon codes 18
Majority voting-based reduced precision redundancy adders 18
Fault tolerant solid state mass memory for space applications 18
Survey of Performance Acceleration Techniques for Network Function Virtualization 18
CuCoTrack: Cuckoo filter based connection tracking 18
Lifetime reliability analysis of complementary resistive switches under threshold and doping interface speed variations 18
Error detection and correction in content addressable memories by using bloom filters 18
Perfect cuckoo filters 18
Smashing OpenFlow's “atomic” actions: Programmable data plane packet manipulation in hardware 17
FPGA oriented design of parity sharing RS codecs 17
Optimization of Self Checking FIR filters by means of Fault Injection Analysis 17
Error detection in addition chain based ECC point multiplication 17
Complementary resistive switch-based arithmetic logic implementations using material implication 17
Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders 17
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation 17
Relaxing state-access constraints in stateful programmable data planes 17
Improving the performance of Invertible Bloom Lookup Tables 17
Reducing the cost of implementing error correction codes in content addressable memories 17
Totale 2174
Categoria #
all - tutte 7588
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 193
selected - selezionate 0
volume - volumi 0
Totale 7781

Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021494 0000 00 00 265821461
2021/20221451 42376333 22533 18114 17118455242
2022/2023882 2801622819 96102 265 8721191
Totale 2827