The memristor is one among the most promising emerging technologies for enabling a new generation of Non Volatile Memories. The memristor operates faster than a Phase Change Memory (PCRAM) and has a simpler structure than a magnetic memory (MRAM), while making possible the design of cross-point structures in crossbars at very high density. The presence of sneak path currents however causes an increase in power consumption and a reduction in data integrity and performance. To overcome this issue a novel write method is proposed to reduce the effects of sneak paths. Extensive SPICE simulations are provided to evidence the advantages of the proposed method.

A Novel Write-Scheme For Data Integrity In Memristor-Based Crossbar Memories / Ruotolo, A; Ottavi, Marco; Pontarelli, Salvatore; Lombardi, F.. - (2012), pp. 168-173. (Intervento presentato al convegno IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) tenutosi a Amsterdam, The Netherlands).

A Novel Write-Scheme For Data Integrity In Memristor-Based Crossbar Memories

PONTARELLI, SALVATORE;
2012

Abstract

The memristor is one among the most promising emerging technologies for enabling a new generation of Non Volatile Memories. The memristor operates faster than a Phase Change Memory (PCRAM) and has a simpler structure than a magnetic memory (MRAM), while making possible the design of cross-point structures in crossbars at very high density. The presence of sneak path currents however causes an increase in power consumption and a reduction in data integrity and performance. To overcome this issue a novel write method is proposed to reduce the effects of sneak paths. Extensive SPICE simulations are provided to evidence the advantages of the proposed method.
2012
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
04 Pubblicazione in atti di convegno::04c Atto di convegno in rivista
A Novel Write-Scheme For Data Integrity In Memristor-Based Crossbar Memories / Ruotolo, A; Ottavi, Marco; Pontarelli, Salvatore; Lombardi, F.. - (2012), pp. 168-173. (Intervento presentato al convegno IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) tenutosi a Amsterdam, The Netherlands).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1523316
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