This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.
F-DICE: a multiple node upset tolerant flip-flop for highly radioactive environments / Campitelli, S., Ottavi, M., Pontarelli, S., Marchioro, A., Felici, D., Lombardi, F.. - (2013), pp. 107-111. (IEEE International Symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT) ) [10.1109/DFT.2013.6653591].
F-DICE: a multiple node upset tolerant flip-flop for highly radioactive environments
Pontarelli S;
2013
Abstract
This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
