Open defects are extremely common in CMOS circuits. They can either be a partial or complete breaking of an input line. The complete breaking of the line is referred to as strong or full open defect. Until few years ago, a full open defect on any interconnecting line has been considered as floating. In nanometric CMOS technology, in which gate leakage currents are not negligible, full open defect lines cannot be considered to be electrically isolated. The final value of the node is independent of the initial state of the node and totally depends on the topological characteristics of the gate. Experimental evidence of the behavior of all basic gates at 90 nm, 64 nm and 32 nm is provided, this shows a decrease in the drain current to gate leakage current ratio, in the technology scaling. The effect of full opens at the gates has also been tested by varying the PVT conditions. These variations provide a range of variation for the full open input voltage and gate leakage current. The effect of full opens on various circuits like the full adder has also been documented at various nanometric levels.
Modeling open defects in nanometric scale CMOS / Hariharan, An; Pontarelli, S; Ottavi, M; Lombardi, F. - (2010), pp. 249-257. (Intervento presentato al convegno IEEE 25th International symposium on defect and fault tolerance in VLSI systems tenutosi a Kyoto; Japan) [10.1109/DFT.2010.37].
Modeling open defects in nanometric scale CMOS
Pontarelli S;
2010
Abstract
Open defects are extremely common in CMOS circuits. They can either be a partial or complete breaking of an input line. The complete breaking of the line is referred to as strong or full open defect. Until few years ago, a full open defect on any interconnecting line has been considered as floating. In nanometric CMOS technology, in which gate leakage currents are not negligible, full open defect lines cannot be considered to be electrically isolated. The final value of the node is independent of the initial state of the node and totally depends on the topological characteristics of the gate. Experimental evidence of the behavior of all basic gates at 90 nm, 64 nm and 32 nm is provided, this shows a decrease in the drain current to gate leakage current ratio, in the technology scaling. The effect of full opens at the gates has also been tested by varying the PVT conditions. These variations provide a range of variation for the full open input voltage and gate leakage current. The effect of full opens on various circuits like the full adder has also been documented at various nanometric levels.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
