ABBAS, ZIA
 Distribuzione geografica
Continente #
EU - Europa 735
NA - Nord America 626
AS - Asia 85
SA - Sud America 2
AF - Africa 1
Continente sconosciuto - Info sul continente non disponibili 1
Totale 1.450
Nazione #
US - Stati Uniti d'America 625
DE - Germania 344
SE - Svezia 175
RU - Federazione Russa 64
IT - Italia 42
AT - Austria 38
CN - Cina 29
IN - India 24
GB - Regno Unito 18
SG - Singapore 15
BG - Bulgaria 13
RO - Romania 13
FI - Finlandia 11
TR - Turchia 10
UA - Ucraina 9
BE - Belgio 4
HK - Hong Kong 2
IE - Irlanda 2
BR - Brasile 1
CA - Canada 1
CL - Cile 1
CZ - Repubblica Ceca 1
EU - Europa 1
FR - Francia 1
KH - Cambogia 1
MA - Marocco 1
MY - Malesia 1
PS - Palestinian Territory 1
TH - Thailandia 1
VN - Vietnam 1
Totale 1.450
Città #
Fairfield 88
Chandler 52
Houston 47
Ashburn 46
Woodbridge 43
Seattle 41
Wilmington 40
Ann Arbor 35
Vienna 34
Cambridge 29
Rome 22
Beijing 21
Plano 21
New York 15
Princeton 15
Boardman 14
San Paolo di Civitate 14
Lawrence 13
Sofia 13
Westminster 13
Istanbul 10
Boston 8
San Diego 8
Singapore 8
Andover 4
Brussels 4
Southend 4
Jacksonville 3
Millbury 3
Dublin 2
Hong Kong 2
Milan 2
Nanjing 2
Norwalk 2
Selargius 2
Baden 1
Baotou 1
Buffalo 1
Bühl 1
Falls Church 1
Hanoi 1
Hanover 1
Hyderabad 1
Indiana 1
Jinan 1
Kaul 1
Kunming 1
Laurel 1
Mcallen 1
Nanchang 1
Phoenix 1
Prague 1
San Mateo 1
Toronto 1
Zhengzhou 1
Totale 700
Nome #
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells 148
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs 140
Current controlled current conveyor (CCCII) and application using 65nm CMOS technology 129
Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations 128
Optimal transistor sizing for maximum yield in variation-aware standard cell design 119
Sizing and optimization of low power process variation aware standard cells 117
Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell 117
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions 110
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) 108
A novel logic level calculation model for leakage currents in digital nano-CMOS circuits 102
LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits 102
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique 96
Yield optimization for low power current controlled current conveyor 83
Design and Fabrication of Microfluidic Chip for Temperature Control Applications in Biomedical 4
Totale 1.503
Categoria #
all - tutte 2.936
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 2.936


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020382 36 25 20 21 32 47 35 43 51 34 30 8
2020/202179 4 23 4 4 0 0 0 10 8 21 5 0
2021/2022258 0 7 18 50 38 15 2 12 23 8 34 51
2022/2023257 43 76 23 14 35 15 11 20 14 1 3 2
2023/202473 4 9 2 3 3 27 1 6 2 3 5 8
2024/20256 6 0 0 0 0 0 0 0 0 0 0 0
Totale 1.503