Catalogo dei prodotti della ricerca

BARBIROTTA, MARCELLO
 Distribuzione geografica
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Continente #
EU - Europa 295
NA - Nord America 106
AS - Asia 66
AF - Africa 4
SA - Sud America 1
Totale 472
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Nazione #
IT - Italia 233
US - Stati Uniti d'America 102
SG - Singapore 51
FI - Finlandia 18
SE - Svezia 12
BG - Bulgaria 7
DE - Germania 6
ES - Italia 5
CA - Canada 4
ID - Indonesia 4
KR - Corea 3
PL - Polonia 3
RU - Federazione Russa 3
UA - Ucraina 3
ZA - Sudafrica 3
AE - Emirati Arabi Uniti 2
CN - Cina 2
FR - Francia 2
IN - India 2
BR - Brasile 1
DZ - Algeria 1
GB - Regno Unito 1
IE - Irlanda 1
IR - Iran 1
JP - Giappone 1
LV - Lettonia 1
Totale 472
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Città #
Rome 116
Singapore 37
Milan 17
Helsinki 15
Chandler 12
Agropoli 9
Fairfield 8
Santa Clara 8
Sofia 7
Aprilia 6
Cambridge 6
Turin 6
Ashburn 5
Jakarta 4
New York 4
San Paolo di Civitate 4
Bilbao 3
Boardman 3
Krakow 3
Lappeenranta 3
Princeton 3
Suwon 3
Toronto 3
Abu Dhabi 2
Albano Laziale 2
Boca Raton 2
Fiumicino 2
Frosinone 2
Lawrence 2
Lugo 2
Macomer 2
Parets del Vallès 2
Salerno 2
Vedano al Lambro 2
Wilmington 2
Woodbridge 2
Agrigento 1
Akishima 1
Altenkirchen 1
Ann Arbor 1
Bologna 1
Buccinasco 1
Bühl 1
Dublin 1
Falkenstein 1
Florence 1
Fort Lee 1
Genazzano 1
Houston 1
Johannesburg 1
Lawrenceville 1
Legnano 1
London 1
Millbury 1
Muizenberg 1
Naples 1
Nuremberg 1
Ottawa 1
Palo del Colle 1
Pastorano 1
Rocca di Papa 1
Silverton 1
Stockholm 1
São Paulo 1
Tivoli 1
Totale 340
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Nome #
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment 76
ADMM consensus for deep LSTM networks 65
Contextual bandits algorithms for reconfigurable hardware accelerators 64
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor 58
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design 32
Fault-tolerant hardware acceleration for high-performance edge-computing nodes 30
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy 30
Improving SET fault resilience by exploiting buffered DMR microarchitecture 29
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core 28
Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor 23
Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors 22
3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool 21
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration 20
Design, implementation and evaluation of a new variable latency integer division scheme 15
Measurements of exhaled CO2 through a novel telemedicine tool 12
AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs 11
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems 7
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach 5
Heterogeneous tightly-coupled dual core architecture against single event effects 4
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design 3
A RISC-V fault-tolerant soft-processor based on full/partial heterogeneous dual-core protection 3
Totale 558
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Categoria #
all - tutte 3.075
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 3.075
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/202137 0 0 0 0 6 1 1 3 3 17 0 6
2021/202236 1 5 1 1 5 0 3 2 7 0 6 5
2022/2023103 8 12 6 3 3 9 0 6 12 11 4 29
2023/2024242 27 17 22 10 23 31 39 17 8 13 17 18
2024/2025140 27 14 33 63 3 0 0 0 0 0 0 0
Totale 558