Improving SET fault resilience by exploiting buffered DMR microarchitecture

Over the past years, several complex redundant systems capable of executing safety applications were developed, with the common purpose of protecting circuits against Single Event Upset (SEU) in sequential logic and Single Event Transient (SET) in combinational logic. Single Event Transients in digital logic set up an ever-growing challenge in reliability design; understanding the SET sensitivity with scaling is necessary to estimate the logic failure and error probability in modern technology generations. The proposed approach uses an experimental Fault Injection campaign with signal glitching to identify SET vulnerability onto different voting strategies, showing how modified versions of N-Modular Redundancy (NMR) react to transient stimuli, using the Klessydra RISC-V processor family as the basis for all the experiments.