Sfoglia per Autore
Mostrati risultati da 1 a 10 di 10
Using safe operation regions to assess the error probability of logic circuits due to process variations
2013 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Sizing and optimization of low power process variation aware standard cells
2013 ABBAS, ZIA; KHALID, USMAN; OLIVIERI, Mauro
Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic
2014 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations
2014 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops
2014 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions
2015 Khalid, Usman; Mastrandrea, Antonio; Abbas, Zia; Olivieri, Mauro
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
2015 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell
2015 Abbas, Zia; Olivieri, Mauro; Khalid, Usman; Ripp, Andreas; Pronath, Michael
RELIABILITY ESTIMATION TECHNIQUES FOR NANOSCALE MOSFETS AND FINFETS CIRCUITS IN THE PRESENCE OF NOISE, VARIABILITY AND AGING
2016 Khalid, Usman
Characterizing noise pulse effects on the power consumption of idle digital cells
2018 Olivieri, M.; Khalid, U.; Mastrandrea, A.; Menichelli, F.
Mostrati risultati da 1 a 10 di 10
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