High yield, reliability, and increasing number of functions in single Integrated Circuit (IC) have been the continuing demand of the market for IC fabrication. However, the uninterrupted scaling of CMOS and FinFET technologies to nano-scale level leads to fallouts in reliability due to the variability of process parameters and the aging caused by Bias Temperature Instability (BTI). Such issues ultimately become responsible for a weakening of noise immunity in digital circuits which translate in higher logic error probability and higher average power consumption. Various types of failures take part in the degradation of circuit reliability when CMOS and FinFET technologies are scaling to nano meter regime. Failures such as input voltage signal fluctuations in presence of additive noise or crosstalk noise within the circuit topology, variations in process parameters of device itself and different aging mechanisms over the lifetime of circuit, can hugely detoriate the reliability of circuit. In this thesis work, several novel modeling techniques such as analytical, semi-analytical and approximation, are introduced in order to quantify failure-probability for both combinational and sequential circuits, in the presence of input voltage noise in conjunction with process variations and aging. Furthermore, an analysis on the impact of noise-induced voltage pulses on the static power consumption of nano-CMOS circuits is implemented by using an approximation model scheme. Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This part of research work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and approximation approaches in comparison with SPICE Monte-Carlo verification approach. Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. The prproposed semi-analytical scheme brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process. Furthermore, the assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis. Last but not least research devoted to the occurrence of noise pulses on the input signals of idle digital cells has been typically associated to reliability issues, such as transient or permanent logic errors. The wide range of possible noise sources in nano-scale circuits, associated to the variability of process parameters, makes it interesting to explore the impact of random voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised by the noise. This part of the thesis proposes a simple yet effective model to characterize the shift in static energy consumption associated to input voltage pulses in logic cells. The characterization scheme allows a fast calculation of the statistical distribution of the energy shift in multi-cell circuits affected by random noise pulses and considering the impact of device statistical variability. The accuracy and effectiveness of the approach have been tested against SPICE simulation, reaching a four orders of magnitude speedup in run time. All of the above proposed techniques were verified against state of the art SPICE Monte Carlo Simulations and results in over 10E4 faster run time with respect to SPICE evaluation.
RELIABILITY ESTIMATION TECHNIQUES FOR NANOSCALE MOSFETS AND FINFETS CIRCUITS IN THE PRESENCE OF NOISE, VARIABILITY AND AGING / Khalid, Usman. - (2016 Apr 22).
RELIABILITY ESTIMATION TECHNIQUES FOR NANOSCALE MOSFETS AND FINFETS CIRCUITS IN THE PRESENCE OF NOISE, VARIABILITY AND AGING
KHALID, USMAN
22/04/2016
Abstract
High yield, reliability, and increasing number of functions in single Integrated Circuit (IC) have been the continuing demand of the market for IC fabrication. However, the uninterrupted scaling of CMOS and FinFET technologies to nano-scale level leads to fallouts in reliability due to the variability of process parameters and the aging caused by Bias Temperature Instability (BTI). Such issues ultimately become responsible for a weakening of noise immunity in digital circuits which translate in higher logic error probability and higher average power consumption. Various types of failures take part in the degradation of circuit reliability when CMOS and FinFET technologies are scaling to nano meter regime. Failures such as input voltage signal fluctuations in presence of additive noise or crosstalk noise within the circuit topology, variations in process parameters of device itself and different aging mechanisms over the lifetime of circuit, can hugely detoriate the reliability of circuit. In this thesis work, several novel modeling techniques such as analytical, semi-analytical and approximation, are introduced in order to quantify failure-probability for both combinational and sequential circuits, in the presence of input voltage noise in conjunction with process variations and aging. Furthermore, an analysis on the impact of noise-induced voltage pulses on the static power consumption of nano-CMOS circuits is implemented by using an approximation model scheme. Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This part of research work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and approximation approaches in comparison with SPICE Monte-Carlo verification approach. Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. The prproposed semi-analytical scheme brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process. Furthermore, the assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting reliability issues caused by aging mechanisms, such as NBTI and PBTI, and variability in process parameters. The effect of such phenomena on system level operation is particularly related to the Static Noise Margins (in idle and read mode) and the Write Noise Margins of memory elements. While Static Noise Margins have been studied in the past, in this work we calculated and compared the effect of process variations and NBTI/PBTI aging on the Write Noise Margins of various MOSFET- and FinFET-based flip-flop cells. The massive transistor-level Monte Carlo simulations produced both nominal (i.e. mean) values and associated standard deviations of the WNMs of the flip-flops. This allowed calculating the consequent write failure probability as a function of an input voltage shift, and assessing a comparison for robustness among different circuit topologies and technologies. Temperature and voltage dependence is also included in the analysis. Last but not least research devoted to the occurrence of noise pulses on the input signals of idle digital cells has been typically associated to reliability issues, such as transient or permanent logic errors. The wide range of possible noise sources in nano-scale circuits, associated to the variability of process parameters, makes it interesting to explore the impact of random voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised by the noise. This part of the thesis proposes a simple yet effective model to characterize the shift in static energy consumption associated to input voltage pulses in logic cells. The characterization scheme allows a fast calculation of the statistical distribution of the energy shift in multi-cell circuits affected by random noise pulses and considering the impact of device statistical variability. The accuracy and effectiveness of the approach have been tested against SPICE simulation, reaching a four orders of magnitude speedup in run time. All of the above proposed techniques were verified against state of the art SPICE Monte Carlo Simulations and results in over 10E4 faster run time with respect to SPICE evaluation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
