Implementing the RISC-V Debug Specification on an Interleaved Multi-Threading Core

Robust on-chip debugging is essential for bringing up, validating, and servicing modern SoCs, but integrating standardized debug into resource-constrained designs can be challenging depending on their structure. This work presents the first standards-compliant integration of the RISC-V External Debug Support Specification v0.13.2 on an Interleaved Multi-threading processor. It features a lightweight 4-state Debug Entity, duplicated CSRs, decode/execute modifications to enable halt, single-step, and abstract-command capabilities. The implementation was done in the 32-bit four-stage Klessydra-T03 core. The FPGA synthesis results on an AMD Xilinx Zynq UltraScale+ ZCU106 show a modest overhead (+20% LUTs, +6.5% FFs, -5.5% fmax), and the modified core passes the full riscv-dbg compliance suite for every hart, both separately and in parallel, providing a concrete blueprint for debug in resource-constrained IMT designs.