Re-Architecting RISC-V: A 64-Bit Take on Interleaved Multi-threading

RISC-V is a rapidly emerging open standard instruction set architecture (ISA), widely adopted in academia for its modularity and extensibility. Among its base ISAs, RV32IM and RV64IM share a common 32-bit instruction encoding but differ significantly in datapath width and associated hardware implications. While transitioning from a 32-bit to a 64-bit RISC-V core may appear straightforward, the hardware overhead remains largely unexplored, especially in interleaved multi-threaded (IMT) cores. To address this gap, we extended the Klessydra T03 core to 64 bit, with and without the M extension, and compared its hardware requirements on a Xilinx Virtex UltraScale VCU108 FPGA with the baseline 32-bit versions. The results show that widening the base architecture to 64 bits nearly doubles the LUTs and FFs utilization (1.98× and 1.95×, respectively), while reducing the maximum operating frequency by 13.5%. With the M extension enabled, LUT, FFs and DSP usage increases by 2.27×, 1.97× and 2.71× respectively, along with a 9.9% frequency drop. Our findings demonstrate that, while RV32IM and RV64IM share instruction formats, the hardware implications of XLEN widening in IMT cores are substantial.