Exploiting the DD-Cell as an ultra-compact entropy source for an FPGA-based re-configurable PUF-TRNG architecture

Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are both needed in the Privacy Preserving Mutual Autentication (PPMA) protocol, often used in IoT Applications to generate and secure cryptographic keys. Since to guarantee security of IoT nodes in an untrusted setting, the PPMA key and encrypted data must be located on the same chip, the concept of integrating both a PUF and a TRNG on the same device has emerged as a new security paradigm. Up to now only a few designs for achieving PUF and TRNG simultaneously on field programmable gate array (FPGA) platforms have been presented in the technical literature, and most of them show sub-optimal performance for one of the two cryptographic primitives. This paper presents a re-configurable design that is able to operate as an FPGA-compatible PUF+TRNG primitive, and relies on the Delay-Difference-Cell (DD-Cell) as the basic entropy source. A theoretical model of the DD-Cell explaining the PUF and the TRNG behaviour of the DD-Cell which highlights the effects of the routing connections on the FPGA on the performances is presented. The proposed solution has been implemented on the Artix-7 FPGA platform, and an extensive measurement campaign involving 32 FPGA boards has been carried out. Measured performances of the proposed PUF and TRNG primitives have been compared against state of the art PUFs and TRNGs, showing performances in line with the state of the art. The comparison against the PUF+TRNG designs available in the literature has shown that the proposed solution exhibits the best trade-off among PUF and TRNG performance, providing the most compact PUF and the highest throughput TRNG.