Inductor-less CMOS filters with bandwidth exceeding several GHz are required in high-speed data converter applications. This paper introduces two complementary biquad filters, one N-based and the other P-based, utilizing the well-established flipped voltage follower (FVF) stage. These filters exhibit more than 7 GHz cut-off frequency and a low power consumption of 0.54 mW/pole for the N-type biquad, and 0.3 mW/pole for the Ptype one, demonstrating impressive figures-of-merit (FOMs) even considering bandwidth and dynamic range. The implementation of these biquads in the STMicroelectronics FD-SOI 28-nm CMOS process, along with extensive simulations, ensures stable performance under process, supply voltage and temperature (PVT) variations and mismatches, as confirmed by post-layout simulations. Notably, the area occupied by each biquad is merely 246 mu m2 2 for N-type biquad and 193 mu m2 2 for P-type, marking one of the smallest footprints in the existing literature. The achieved figures-of-merit are noteworthy, showcasing excellent power efficiency, minimal area occupation, and commendable dynamic range.
A novel FVF-based GHz-range biquad in a 28 nm CMOS FD-SOI technology / Lombardo, Matteo; Centurelli, Francesco; Monsurro', Pietro; Trifiletti, Alessandro. - In: AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS. - ISSN 1434-8411. - 185:(2024). [10.1016/j.aeue.2024.155466]
A novel FVF-based GHz-range biquad in a 28 nm CMOS FD-SOI technology
Lombardo, Matteo;Centurelli, Francesco;Monsurro', Pietro;Trifiletti, Alessandro
2024
Abstract
Inductor-less CMOS filters with bandwidth exceeding several GHz are required in high-speed data converter applications. This paper introduces two complementary biquad filters, one N-based and the other P-based, utilizing the well-established flipped voltage follower (FVF) stage. These filters exhibit more than 7 GHz cut-off frequency and a low power consumption of 0.54 mW/pole for the N-type biquad, and 0.3 mW/pole for the Ptype one, demonstrating impressive figures-of-merit (FOMs) even considering bandwidth and dynamic range. The implementation of these biquads in the STMicroelectronics FD-SOI 28-nm CMOS process, along with extensive simulations, ensures stable performance under process, supply voltage and temperature (PVT) variations and mismatches, as confirmed by post-layout simulations. Notably, the area occupied by each biquad is merely 246 mu m2 2 for N-type biquad and 193 mu m2 2 for P-type, marking one of the smallest footprints in the existing literature. The achieved figures-of-merit are noteworthy, showcasing excellent power efficiency, minimal area occupation, and commendable dynamic range.File | Dimensione | Formato | |
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