Robust body biasing techniques for dynamic comparators

Forward body biasing (FBB) is among the simplest and most effective techniques that can be leveraged to improve the performance of dynamic comparators, as previous works have demonstrated. However, none of these works puts emphasis on comparing different FBB schemes and their robustness against large differential input swings. This is especially important when considering circuits that operate at supply voltages above 0.5 V, where several approaches can be adopted for biasing the substrates without causing the body-source junctions to turn on. This paper compares three different techniques: the clocked FBB (CFBB) proposed in [1], an improvement of CFBB and a new hybrid approach that achieves the best performance in terms of delay. For the sake of brevity, the scope of our experiments has been limited to the Strong Arm latch. All simulations were carried out in a 55 nm CMOS technology at 1 V supply and 2.4 GHz clock frequency.