In this work a novel ultra-low voltage, ultra-low power fully synthesizable comparator is presented. The proposed architecture exploits only 2-input NAND gates, that allow minimization of the area footprint and scalability up to extremely low supply voltages. An extensive simulation campaign in a 130 nm CMOS technology has shown state-of-the-art performance in terms of power-delay-product for supply voltages down to 0.3V. Simulations also show good robustness under mismatch and PVT variations, proving the feasibility of the approach.
A novel ultra-low voltage fully synthesizable comparator exploiting NAND gates / Della Sala, R; Bocciarelli, C; Centurelli, F; Spinogatti, V; Trifiletti, A. - (2023), pp. 21-24. (Intervento presentato al convegno PRIME 23. 18th International conference on Ph.D. research in microelectronics and electronics tenutosi a Valencia; Spain) [10.1109/PRIME58259.2023.10161936].
A novel ultra-low voltage fully synthesizable comparator exploiting NAND gates
Della Sala, R;Bocciarelli, C;Centurelli, F;Spinogatti, V;Trifiletti, A
2023
Abstract
In this work a novel ultra-low voltage, ultra-low power fully synthesizable comparator is presented. The proposed architecture exploits only 2-input NAND gates, that allow minimization of the area footprint and scalability up to extremely low supply voltages. An extensive simulation campaign in a 130 nm CMOS technology has shown state-of-the-art performance in terms of power-delay-product for supply voltages down to 0.3V. Simulations also show good robustness under mismatch and PVT variations, proving the feasibility of the approach.File | Dimensione | Formato | |
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