In this work we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, and gates to derive a basic building block, namely basic amplifier (BA) cell, which is equivalent to a CMOS inverter (used as a transconductance amplifier) with an additional input which allows to accurately set its static output voltage and to obtain a balanced input-output voltage transfer characteristic. We propose also a standard-cell-based control loop based on a replica bias technique which, despite PVT variations, allows to guarantee a static output voltage equal to half the supply voltage for all the BA cells used in the analog section of the chip. The approach has been validated through parametric and corner simulations referring to a 130 nm CMOS process and the performed analyses have highlighted that the proposed BA cell attains reliable performance under PVT variations, whereas the conventional inverter gate taken from the standard-cell library performs in a very unreliable way in the same PVT conditions.

Enabling ULV Fully Synthesizable Analog Circuits: the BA Cell, a Standard-Cell-Based Building Block for Analog Design / DELLA SALA, Riccardo; Centurelli, Francesco; Scotti, Giuseppe.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - (2022), pp. 1-5. [10.1109/TCSII.2022.3199250]

Enabling ULV Fully Synthesizable Analog Circuits: the BA Cell, a Standard-Cell-Based Building Block for Analog Design

Della Sala Riccardo
Primo
;
Centurelli Francesco
Secondo
;
Scotti Giuseppe.
Ultimo
2022

Abstract

In this work we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, and gates to derive a basic building block, namely basic amplifier (BA) cell, which is equivalent to a CMOS inverter (used as a transconductance amplifier) with an additional input which allows to accurately set its static output voltage and to obtain a balanced input-output voltage transfer characteristic. We propose also a standard-cell-based control loop based on a replica bias technique which, despite PVT variations, allows to guarantee a static output voltage equal to half the supply voltage for all the BA cells used in the analog section of the chip. The approach has been validated through parametric and corner simulations referring to a 130 nm CMOS process and the performed analyses have highlighted that the proposed BA cell attains reliable performance under PVT variations, whereas the conventional inverter gate taken from the standard-cell library performs in a very unreliable way in the same PVT conditions.
2022
Computer architecture; Fully Synthesizable; Inverter-Based; Inverters; Logic gates; Performance evaluation; Standard-Cell; Transconductance; Transistors; Ultra-Low-Voltage; Voltage control
01 Pubblicazione su rivista::01a Articolo in rivista
Enabling ULV Fully Synthesizable Analog Circuits: the BA Cell, a Standard-Cell-Based Building Block for Analog Design / DELLA SALA, Riccardo; Centurelli, Francesco; Scotti, Giuseppe.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - (2022), pp. 1-5. [10.1109/TCSII.2022.3199250]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1654882
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