This paper presents the design of a low-noise, low-power transimpedance amplifier (TIA) for biomedical applications. The proposed TIA exploits for the first time in the literature a Switched–Resistor (SR) as the feedback element in order to achieve a digitally tunable transimpedance gain with an extremely large tuning range (higher than 80 dB) and a maximum value as high as 10 GΩ. Another important feature which comes with the adoption of the SR technique is that the output voltage is already sampled with the SR clock signal and this simplifies the design of the following digitizer block. The circuit has been designed in a commercial 130 nm CMOS technology and simulation results show a minimum IRCSN (input-referred current spectrum noise) of 1.67 fA/√Hz and a total power consumption of 0.9 μW with a 0.6 V supply voltage. Extensive parametric and Monte Carlo simulations have confirmed a good robustness against PVT and mismatch variations.
80 dB tuning range transimpedance amplifier exploiting the Switched-Resistor approach / Centurelli, Francesco; Fava, Alessandro; Scotti, Giuseppe; Trifiletti, Alessandro. - In: AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS. - ISSN 1434-8411. - 149:(2022). [10.1016/j.aeue.2022.154196]
80 dB tuning range transimpedance amplifier exploiting the Switched-Resistor approach
Centurelli, Francesco;Fava, Alessandro;Scotti, Giuseppe;Trifiletti, Alessandro
2022
Abstract
This paper presents the design of a low-noise, low-power transimpedance amplifier (TIA) for biomedical applications. The proposed TIA exploits for the first time in the literature a Switched–Resistor (SR) as the feedback element in order to achieve a digitally tunable transimpedance gain with an extremely large tuning range (higher than 80 dB) and a maximum value as high as 10 GΩ. Another important feature which comes with the adoption of the SR technique is that the output voltage is already sampled with the SR clock signal and this simplifies the design of the following digitizer block. The circuit has been designed in a commercial 130 nm CMOS technology and simulation results show a minimum IRCSN (input-referred current spectrum noise) of 1.67 fA/√Hz and a total power consumption of 0.9 μW with a 0.6 V supply voltage. Extensive parametric and Monte Carlo simulations have confirmed a good robustness against PVT and mismatch variations.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.