A detailed model of the switched-resistor technique

The Switched-Resistor (S-R) approach is gaining popularity among integrated circuits designers because it allows to implement very high equivalent resistances, and thus very large time constants, in CMOS circuits. In this paper, we present an in-depth analysis of the S-R technique and propose a novel detailed model which allows to accurately predict the value of the equivalent resistance even for values of the duty cycle as low as 0.0001% which result in a huge resistance multiplication factor. We show that the conventional model of the S-R technique provides a reasonable accuracy for duty cycle values down to 1%, but its accuracy becomes unacceptable for smaller values of the duty cycle. In the proposed detailed model of the S-R we take into account also the parasitic capacitances of the integrated poly resistors and the non-ideal resistance of the CMOS switches. The modeling strategy is based on the solution of the differential equations for the different switches settings and exploits the Y-matrix to represents the floating S-R. The proposed model has been validated against periodic steady state (PSS) and periodic AC (PAC) simulations referring to a 130nm CMOS technology. Results have shown an average and maximum error lower than 0.53% and 5.15% respectively. As a further validation, a first-order active low-pass filter has been implemented with the same technology with a cutoff frequency tunable from 1.68Hz to 1.46kHz. The average and maximum errors in the estimation of the cutoff frequency have resulted lower than 3.6% and 7% respectively.